FPGA Implementation of An Array Processor.

Authors

• Faris M., Control & Systems Engineering/University of Technology Baghdad, Iraq

Document Type

Original Study

Abstract

This paper describes how to map the array processor to the Xilinx Field Programmable Gate Array (FPGA) Chip. The design is connected to personal computer and tested as a matrix multiplication using a high level (Visual Basic) program. The developed conVolution architecture was captured through the use of the Very High Scale Hardware Description Language (VHDL). Xilinx Foundation series (4.1i) Computer Aided Design (CAD) software package was used to synthesize and implement the architecture of the array processor to the FPGA chip. Before the architecture was prototyped into the prototyping board for experimental testing, the architecture was functionally and performance validated through Hardware Description Language (HDL) software simulation via post-synthesis and post-implementation software simulations.

How to Cite This Article

M., Faris (2006) "FPGA Implementation of An Array Processor.," Iraqi Journal of Computers, Communications, Control and Systems Engineering: Vol. 6: Iss. 1, Article 6.
Available at: https://ijccce.researchcommons.org/journal/vol6/iss1/6